1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a flash memory.
2. Description of the Related Art
A conventional flash memory is a type of erasable programmable read-only memory (EPROM), which in turn is a type of non-volatile memory. In general, an EPROM cell comprises two gates. One of the gates, known as a floating gate, is fabricated from polysilicon and is used for charge storage. The second gate, known as the control gate, is used for controlling the input and output of data. The above floating gate is located beneath the control gate, and is generally in a floating state because there is no connection with external circuits. The control gate is normally wired to the word line. One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, the speed of memory erase is fast, and normally takes just 1 to 2 seconds for the complete removal of a whole block of memory. For most other EPROM, memory erasure can take up to several minutes due to its bit-by-bit operation.
In typical integrated circuits (ICs), two adjacent devices should be isolated from each other by an insulating structure such as a filed oxide layer or a shallow trench isolation (STI). The STI is better than the field oxide layer and the size of the devices can be decreased by using the STI, so the STI is more popular than the field oxide layer in IC industry. Currently, the STI is formed by first anisotropically etching to form a trench in the substrate, and then depositing an oxide layer in the trench and over the substrate. Next, a chemical-mechanical polishing step is used to planarize the oxide layer to finish the process of manufacturing the STI.
However, the flash memory with the STI structures has the problem of misalignment while the STI of the flash memory is formed. The misalignment leads to unanticipated electrical coupling and relatively low reliability of the devices. Additionally, the size of the devices is limited by the design rule, so it is difficult to reduce the size of the devices.